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september 2009 ? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers fin1215 / fin1216 / fin1217/ fin1218 lvds 21-bit serializers / de-serializers features ? low power consumption ? 20mhz to 85mhz shift clock support ? 50% duty cycle on the clock output of receiver ? 1v common-mode range ~1.2v ? narrow bus reduces cable size and cost ? high throughput: 1.785gbps ? up to 595mbps per channel ? internal pll with no external components ? compatible with tia/eia-644 specification ? offered in 48-lead tssop packages description the fin1217 and fin1215 transform 21-bit wide parallel lvttl (low-voltage ttl) data into three serial lvds (low-voltage differential signaling) data streams. a phase-locked transmi t clock is transmitted in parallel with the data stream over a separate lvds link. every cycle of transmit clock, 21 bits of input lvttl data are sampled and transmitted. the fin1216 and fin1218 receives and converts the three serial lvds data streams back into 21 bits of lvttl data. table 1 provides a matrix summary of the serializers and de-serializers available. for the fin1217, at a transmit clock frequency of 85mhz, 21 bits of lvttl data are transmitted at a rate of 595mbps per lvds channel. these chipsets solve emi and cable size problems associated with wide and high-speed ttl interfaces. ordering information part number operating temperature range eco status package packing method FIN1215MTDX -40 to + 85c rohs 48-lead thin shrink small outline package (tssop) tape and reel fin1216mtdx fin1217mtdx fin1218mtdx (preliminary) for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 2 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers block diagrams figure 1. fin1217 / fin1215 transmitter functional diagram figure 2. fin1218 / fin1216 receiver functional diagram table 1. serializers / de-serializers chip matrix part clk frequency lvttl in lvds out lvds in lvttl out package fin1215 66 21 3 48-lead tssop fin1216 66 3 21 48-lead tssop fin1217 85 21 3 48-lead tssop fin1218 85 3 21 48-lead tssop
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 3 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers transmitters pin configuration figure 3. fin1217 / fin1215 (21:3 transmitter) pin definitions pin names i/o type # of pins description of signals txin i 21 lvttl level inputs txcklin i 1 lvttl level clock input; the rising edge is for data strobe txout+ o 3 positive lvds differential data output txout o 3 negative lvds differential data output txclkout+ o 1 positive lvds differential clock output txclkout- o 1 negative lvds differential clock output /pwrdn i 1 lvttl level power-down input; assertion (low) puts the outputs in high- impedance state pll v cc i 1 power supply pin for lvds outputs pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pins for lvds outputs lvds gnd i 3 ground pin for lvds outputs v cc i 4 power supply pins for lvttl inputs gnd i 5 ground pins for lvttl inputs nc no connect
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 4 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers receivers pin configuration figure 4. fin1216 / fin1218 (3:21 receiver) pin definitions pin names i/o type # of pins description of signals rxin i 3 negative lvds differential data output rxin+ i 3 positive lvds differential data output rxclkin- i 1 negative lvds differential clock output rxclkin+ i 1 positive lvds differential clock output rxout- o 21 lvttl level data outputs goes high for /pwrdn low rxclkout o 1 lvttl level clock output /pwrdn i 1 lvttl level input; refer to transmitter and receiver power-up and power-down operation truth table pll v cc i 1 power supply pin for pll pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pins for lvds inputs lvds gnd i 3 ground pin for lvds inputs v cc i 4 power supply pins for lvttl outputs gnd i 5 ground pins for lvttl outputs nc no connect
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 5 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers truth tables transmitter inputs outputs txin txclkin pwrdn (1) txout txclkout active active high low / high low / high active low / high high impedance high low / high don?t care (2) floating active high low low / high floating floating high low don?t care (2) don?t care don?t care low high impedance high impedance notes : 1. the outputs of the transmitter or receiv er remain in a high-impedance state until v cc reaches 2v. 2. txclkout settles at a free running frequency when the par t is powered up, pwrdn is high and the txclkin is a steady logic level low / high / high-impedance. receiver inputs outputs rxin rxclkin /pwrdn (3) rxout rxclkout active active high low / high low / high active failsafe condition (4) high last valid state high failsafe condition (4) active high high low / high failsafe condition (4) failsafe condition (4) high last valid state (5) high don?t care don?t care low low high notes : 3. the outputs of the transmitter or receiv er remain in a high-impedance state until v cc reaches 2v. 4. failsafe condition is defined as the input being terminated and un-driven, shorted, or open. 5. if rxclkin is removed prior to the rxin date being removed, rxout is the last valid state. if rxin data is removed prior to rxclkin being removed, rxout is high.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 6 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc power supply voltage -0.3 +4.6 v v ttl ttl/cmos input/output voltage -0.5 +4.6 v v lvds lvds input/output voltage -0.3 +4.6 v i osd lvds output short-circuit current continuous t stg storage temperature range -65 +150 c t j maximum junction temperature, soldering 4 seconds +150 c t l lead temperature +260 c esd human body model, jesd22-a114 (1.5k , 100pf) lvds i/o to ground 10.0 kv all pins (fin1215, fin1217) 6.5 machine model, jesd22-a115, 0 , 200pf fin1215, fin1217 only >400 v recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a operating temperature -40 +85 c v ccnpp maximum supply noise voltage (6) 100 mv pp note : 6. 100mv v cc noise should be tested for frequency at least up to 2mhz. all the specifications should be met under such a noise level.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 7 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers transmitter dc electrical characteristics typical values are at t a =25c and with v cc =3.3v; minimum and maximum are at over supply voltages and operating temperatures ranges, unle ss otherwise specified. symbol parameter test conditions min. typ. max. units transmitter lvttl input characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v ik input clamp voltage i ik =-18ma -0.79 -1.50 v i in input current v in =0.4v to 4.6v 1.8 10.0 a v in =gnd -10.0 0 transmitter lvds output characteristics (7) v od output differential voltage r l =100 , figure 4 250 450 mv v od v od magnitude change from differential low-to-high 35 mv v os offset voltage 1.125 1.250 1.375 v v os offset magnitude change from differential low-to-high 25 mv i os short-circuit output current v out =0v -3.5 -5.0 ma i oz disabled output leakage current d o =0v to 4.6v, /pwrdn=0v 1.0 10.0 a transmitter supply current i ccwt 21:3 transmitter power supply current for worst-case pattern with load (8, 9) r l =100 , figure 7 33mhz 28.0 46.2 ma 40mhz 29.0 51.7 65mhz 34.0 57.2 85mhz (10) 39.0 62.7 i ccpdt powered-down supply current /pwrdn=0.8v 10.0 55.0 a notes : 7. positive current values refer to the current flowing into device and negative values means current flowing out of pins. voltages are referenced to ground unless otherwise specified (except v od and v od ). 8. the power supply current for both transmitter and receiv er can be different with the number of active i/o channels. 9. the 16-grayscale test pattern tests device power cons umption for a ?typical? lcd display pattern. the test pattern approximates signal switching needed to produce gr oups of 16 vertical strips across the display. 10. fin1217 only.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 8 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers transmitter ac electrical characteristics typical values are at over supply voltages and operati ng temperatures ranges, unle ss otherwise specified. symbol parameter conditions min. typ. max. units t tcp transmit clock period figure 10 11.76 t 50.00 ns t tch transmit clock (txclkin) high time 0.35 0.50 0.65 t t tcl transmit clock low time 0.35 0.50 0.65 t t clkt txclkin transition time (rising and falling) 10% to 90% figure 11 1.0 6.0 ns t jit txclkin cycle-to-cycle jitter 3.0 ns t xit txin transition time 1.5 6.0 ns lvds transmitter timing characteristics t tlh differential output rise time (20% to 80%) figure 8 0.75 1.50 ns t thl differential output fall time (80% to 20%) 0.75 1.50 ns t stc txin setup to txclnin figure 10 f=85mhz fin1217 only 2.5 ns t htc txin holds to tclkin 0 ns t tpdd transmitter power-down delay figure 17 (11) 100 ns t tccd transmitter clock input to clock output delay figure 13 t a =25c, v cc =3.3v 2.8 5.5 6.8 ns transmitter output data jitter (f=40 mhz) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a = -0.25 0 0.25 ns t tppb1 transmitter output pulse position of bit 1 a-0.25 a a+0.25 ns t tppb2 transmitter output pulse position of bit 2 2a-0.25 2a 2a+0.25 ns t tppb3 transmitter output pulse position of bit 3 3a-0.25 3a 3a+0.25 ns t tppb4 transmitter output pulse position of bit 4 4a-0.25 4a 4a+0.25 ns t tppb5 transmitter output pulse position of bit 5 5a-0.25 5a 5a+0.25 ns t tppb6 transmitter output pulse position of bit 6 6a-0.25 6a 6a+0.25 ns transmitter output data jitter (f=65 mhz) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a = -0.2 0 0.2 ns t tppb1 transmitter output pulse position of bit 1 a-0.2 a a+0.2 ns t tppb2 transmitter output pulse position of bit 2 2a-0.2 2a 2a+0.2 ns t tppb3 transmitter output pulse position of bit 3 3a-0.2 3a 3a+0.2 ns t tppb4 transmitter output pulse position of bit 4 4a-0.2 4a 4a+0.2 ns t tppb5 transmitter output pulse position of bit 5 5a-0.2 5a 5a+0.2 ns t tppb6 transmitter output pulse position of bit 6 6a-0.2 6a 6a+0.2 ns continued on following page?
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 9 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers transmitter ac electrical characteristics (continued) symbol parameter conditions min. typ. max. units transmitter output data jitter (f=85 mhz, fin1217 only) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a = -0.2 0 0.2 ns t tppb1 transmitter output pulse position of bit 1 a-0.2 a a+0.2 ns t tppb2 transmitter output pulse position of bit 2 2a-0.2 2a 2a+0.2 ns t tppb3 transmitter output pulse position of bit 3 3a-0.2 3a 3a+0.2 ns t tppb4 transmitter output pulse position of bit 4 4a-0.2 4a 4a+0.2 ns t tppb5 transmitter output pulse position of bit 5 5a-0.2 5a 5a+0.2 ns t tppb6 transmitter output pulse position of bit 6 6a-0.2 6a 6a+0.2 ns t jcc transmitter clock out jitter, cycle-to cycle figure 23 f=40mhz 350 370 ps f=65mhz 210 230 f=85mhz fin1217 only 110 150 t tplls transmitter phase lock loop set time (13) figure 15 (12) 10.0 ms notes : 11. outputs of all transmitters stay in 3-state until power reaches 2v. clock and data output begins to toggle 10ms after v cc reaches 3v and /pwrdn pin is above 1.5v. 12. this output data pulse position works for both transmi tters with 21 ttl inputs, except the lvds output bit mapping difference (see figure 19). figure 20 shows t he skew between the first data bit and clock output. a two-bit cycle delay is guaranteed when the msb is output from transmitter. 13. this jitter specification is based on the assumption that pll has a reference clock with cycle-to-cycle input jitter of less than 2ns.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 10 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers receiver dc electrical characteristics typical values are at t a =25c and with v cc =3.3v. positive current values refer to the current flowing into device and negative values means current flowing out of pins. volt ages are referenced to ground unless otherwise specified (except v od and v od ). minimum and maximum values are at over supply voltage and operating temperature ranges unless otherwise specified. symbol parameter conditions min. typ. max. units lvttl/cmos dc characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v oh output high voltage i oh =-0.4ma 2.7 3.3 v v ol output low voltage i ol =2ma 0.3 v v ik input clamp voltage i ik =-18ma -1.5 v i in input current v in =0v to 4.6v -10 10 a i off input/output power-off leakage current v cc =0v, all lvttl inputs/outputs 0v to 4.6v 10 a i os output short-circuit current v out =0v -60 -120 a receiver lvds input characteristics v th differential input threshold high figure 6, table 2 100 mv v tl differential input threshold low figure 6, table 2 -100 mv v icm input common mode range figure 6, table 2 0.05 2.35 v i in input current v in =2.4v, v cc =3.6v or 0v 10.0 a v in =0v, v cc =3.6v or 0v 10.0 receiver supply current i ccwr 3:21 receiver power supply current for worst case pattern with load (14) c l =8pf, figure 7 33mhz 66 ma 40mhz 56 74 65mhz 75 102 85mhz (15) 92 125 i ccpdr powered down supply current /pwrdn=0.8v (rxout stays low) na 400 a notes : 14. the power supply current for the receiver can be different due to the number of active i/o channels. 15. 85mhz specification for fin1218 only.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 11 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers receiver ac electrical characteristics values are at over supply voltages and operati ng temperatures, unless otherwise specified. symbol parameter conditions min. typ. max. units t rcol rxclkout low time figure 12 rising edge strobe f=40mhz 10.0 11.0 ns t rcoh rxclkout high time 10.0 12.2 ns t rsrc rxout valid prior to rxclkout 6.5 11.6 ns t rhrc rxout valid after rxclkout 6.0 11.6 ns t rcop receiver clock output (rxclkout) period figure 12 rising edge strobe f=65mhz 15.0 t 50.0 ns t rcol rxclkout low time 5.0 7.8 9.0 ns t rcoh rxclkout high time 5.0 7.3 9.0 ns t rsrc rxout valid prior to rxclkout 4.5 7.7 ns t rhrc rxout valid after rxclkout 4.0 8.4 ns t rcop receiver clock output (rxclkout) period figure 12 rising edge strobe f=85mhz fin1218 only 11.76 t 50.00 ns t rcol rxclkout low time 4.0 6.3 6.0 ns t rcoh rxclkout high time 4.5 5.4 6.5 ns t rsrc rxout valid prior to rxclkout 3.5 6.3 ns t rhrc rxout valid after rxclkout 3.5 6.5 ns t rolh output rise time (20% to 80%) c l =8pf, figure 9 2.2 5.0 ns t rohl output fall time (80% to 20%) 2.1 5.0 ns t rccd receiver clock input to clock output delay t a =25c, v cc =3.3v figure 14 ( error! reference source not found. ) 3.5 6.9 7.5 ns t rpdd receiver power-down delay figure 18 1.0 ms t rspb0 receiver input strobe position of bit 0 figure 21 f=40mhz 1.00 2.15 ns t rspb1 receiver input strobe position of bit 1 4.5 5.8 ns t rspb2 receiver input strobe position of bit 2 8.10 9.15 ns t rspb3 receiver input strobe position of bit 3 11.6 12.6 ns t rspb4 receiver input strobe position of bit 4 15.1 16.3 ns t rspb5 receiver input strobe position of bit 5 18.8 19.9 ns t rspb6 receiver input strobe position of bit 6 22.5 23.6 ns continued on following page?
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 12 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers receiver ac electrical characteristics (continued) symbol parameter conditions min. typ. max. units t rspb0 receiver input strobe position of bit 0 figure 21 f=65mhz 0.7 1.4 ns t rspb1 receiver input strobe position of bit 1 2.9 3.6 ns t rspb2 receiver input strobe position of bit 2 5.1 5.8 ns t rspb3 receiver input strobe position of bit 3 7.3 8.0 ns t rspb4 receiver input strobe position of bit 4 9.5 10.2 ns t rspb5 receiver input strobe position of bit 5 11.7 12.4 ns t rspb6 receiver input strobe position of bit 6 13.9 14.6 ns t rspb0 receiver input strobe position of bit 0 figure 21 f=85mhz fin1218 only 0.49 1.19 ns t rspb1 receiver input strobe position of bit 1 2.17 2.87 ns t rspb2 receiver input strobe position of bit 2 3.85 4.55 ns t rspb3 receiver input strobe position of bit 3 5.53 6.23 ns t rspb4 receiver input strobe position of bit 4 7.21 7.91 ns t rspb5 receiver input strobe position of bit 5 8.89 9.59 ns t rspb6 receiver input strobe position of bit 6 10.57 11.27 ns t rskm rxin skew margin ( error! reference source not found. ) f=40mhz, figure 22 490 ps f=65mhz, figure 22 400 f=85mhz fin1218 only figure 22 252 t rplls receiver phase lock loop set time figure 16 10.0 ms notes: 16. total channel latency from seria lizer to deserializer is (t + t tccd ) + (2?t + t rccd ). 17. receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 13 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers test circuits figure 5. differential lvds output dc test circuit notes: for all input pulses, t r or t f <=1ns. c l includes all probe and jig capacitance. figure 6. differential receiver voltage definitions, propagation delay, and transition time test circuit table 2. receiver minimum and maximum input threshold test voltages applied voltages (v) resulting differential input voltage (mv) resulting common mode input voltage (v) v ia v ib v id v ic 1.25 1.15 100 1.20 1.15 1.25 -100 1.20 2.40 2.30 100 2.35 2.30 2.40 -100 2.35 0.10 0 100 0.05 0 0.10 -100 0.05 1.50 0.90 600 1.20 0.90 1.50 -600 1.20 2.40 1.80 600 2.10 1.80 2.40 -600 2.10 0.60 0 600 0.30 0 0.60 -600 0.30
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 14 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers ac loadings and waveforms note: the worst-case test pattern produces a maximum t oggling of digital circuits, lvds i/o and lvttl/cmos i/o. depending on the valid strobe edge of transmitter, the txcl kin can be either rising or failing edge data strobe. figure 7. worst-case test pattern figure 8. transmitter lvds ou tput load and transition times figure 9. receiver lvttl/cmos output load and transition times figure 10. transmitter set-up/hold and high/low times (rising edge strobe) figure 11. transmitter input clock transition time
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 15 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers ac loadings and waveforms (continued) figure 12. receiver set-up/hold and high/low times figure 13. transmitter clock-in to cl ock-out delay (rising edge strobe) figure 14. receiver clock-in to clock-out delay (rising edge strobe) figure 15. transmitter phase-lock-loop set time
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 16 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers ac loadings and waveforms (continued) figure 16. receiver phase lock loop set time figure 17. transmitter power-down delay figure 18. receiver power-down delay note: this output date pulse position works for both transmi tters with 21 ttl inputs, except the lvds output bit mapping difference. two-bit cycle delay is guarant eed with the msb is output from transmitter. figure 19. parallel lvttl inputs mappe d to three serial lvds outputs
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 17 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers ac loadings and waveforms (continued)] figure 20. transmitter output pulse bit position figure 21. receiver strobe bit position
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 18 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers ac loadings and waveforms (continued) note: t rskm is the budget for the cable skew and source clo ck skew plus inter-symbol interference (isi). the minimum and maximum pulse position values are based on the bit position of each of the seven bits within the lvds data stream across pvt (pro cess, voltage supply, and temperature). figure 22. receiver lvds input skew margin note: this jitter pattern is used to te st the jitter response (clock out) of the device over the power supply range with worst jitter ns (cycle-to-cycle) clock input. the specific test methodology is as follows: ? switching input data txin0 to txin20 at 0.5mhz and the input clock is shifted to left -3ns and to the right +3ns when data is high (by switching between clk1 and clk2 in figure 11) . ? the 3ns cycle-to-cycle input jitter is the st atic phase error between the two clock sources. jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from graphical controllers. cycle-to-cycle jitter at txclk out pin should be measured cross v cc range with 100mv noise (v cc noise frequency <2mhz). figure 23. jitter pattern
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 19 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers physical dimensions figure 24. 48-lead thin shrink small outline package (tssop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1215 / fin1216 / fin1217 ? rev. 1.0.3 20 fin1215 / fin1216 / fin1217 ? lvds 21-bit serializers / de-serializers

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